Keynote

Understanding performance and energy efficiency trade-offs under power capping and frequency scaling scenarios

  • Hager, Georg (Friedrich-Alexander-Universitaet Erlangen-Nue)
  • Mayr, Martin (Friedrich-Alexander-Universitaet Erlangen-Nue)
  • Ujeniya, Aditya (Friedrich-Alexander-Universitaet Erlangen-Nue)
  • Wellein, Gerhard (Friedrich-Alexander-Universitaet Erlangen-Nue)

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Power consumption of high-performance computing (HPC) systems is steadily increasing. The strong demand of simulation sciences and AI/ML for HPC resources is putting their energy consumption at critical levels both economically and ecologically. From an operational perspective, a major power-saving mechanism is frequency scaling or power capping. As this may interfere with application runtime it is not clear if overall energy consumption at the application level is reduced at all. It is well known that the interaction of power capping, processor frequencies, application runtime and energy consumption is complex and depends on numerous parameters including application performance bottlenecks, chip production technology, and chip quality. This presentation will review basic energy efficiency metrics and the most important guidelines for power capping / frequency scaling in the context of application bottlenecks such as memory bandwidth or core execution speed. It will analyse the intricate interaction of power capping, CPU-/GPU-frequency, runtime and various efficiency metrics on state-of-the art HPC hardware, including high-core count CPUs and latest GPUs including NVIDIA’s Hopper and Blackwell architecture. The discussion will cover simple benchmark kernels as well as full applications from simulation sciences and AI/ML.